計算機言語談話会(CLC) Computer Language Colloquium


計算機言語談話会(Computer Language Colloquium, 略称 CLC)は、 計算機言語(プログラミング言語、仕様記述言語、証明記述言語その他)に関 する理論、言語設計、処理系作成などの研究の話を産総研内外の人にしていた だくためのものです。 どなたでも御来聴を歓迎します。




日時 平成 23 年 2 月 7 日 (月) 15:00-17:00
場所 (独)産総研関西センター尼崎事業所E棟1階小セミナー室
TALK1: SAT based debug
Prof. Andreas Aveneris (the University of Toronto)
概題 SAT-based multiple fault diagnosis for combinational and sequential circuits
- Benefits from advances to SAT solvers
- Formulation is intuitive and easy to implement
- Captures significant characteristics of the diagnosis and debugging    problems Motivates future work
- Find diagnosis-specific SAT enhancements
- Model-based diagnosis
- Enhance the debugging technique as a complementary process to    verification
演題 TALK2: QBF (Quantified Boolean Formula satisfiability)

Formal CAD tools operate on mathematical models describing the sequential behavior of a VLSI design. With the growing size and state-space of modern digital hardware designs, the conciseness of this mathematical model is of paramount importance in extending the scalability of those tools, provided that the compression does not come at the cost of reduced performance.

Quantified Boolean Formula satisfiability (QBF) is a powerful generalization of Boolean satisfiability (SAT). It also belongs to the same complexity class as many CAD problems dealing with sequential circuits, which makes it a natural candidate for encoding such problems. This work proposes a succinct QBF encoding for modeling sequential circuit behavior. The encoding is parametrized and further compression is achieved using time-frame windowing. Comprehensive hardware constructions are presented to illustrate the proposed encodings. Three notable CAD problems, namely bounded model checking, design debugging and sequential test pattern generation, are encoded as QBF instances to demonstrate the robustness and practicality of the proposed approach.

Unlike previous QBF-based encodings for verification problems, the presented work provides a general-purpose QBF-based ILA representation for a multitude of CAD applications. It is designed to reduce memory requirements but also achieve competitive run-times when compared to state-of-the-art SAT. Indeed, extensive experiments on OpenCore circuits show memory reductions in the order of 90% and demonstrate competitive run-times compared to state-of-the-art SAT techniques. Furthermore, the number of solved instances is increased by 16%. Admittedly, this work encourages further research in the use of QBF in CAD for VLSI.



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